| 摘要 |
PURPOSE:To decrease a clock speed, by shifting the counted value of an up/ down counter down when a detection range is less than a set value, and setting only the shifted-down high-order digits in a down counter. CONSTITUTION:A selector 66 is provided between the up/down counter 25 and down counter 26. When a detection range setting signal supplied from a terminal 29 to a detecting circuit 67 is greater than a specific value, the selector 66 sets the counted contents which are shifted down by two bits in the counter 26. When the output of the detecting circuit 67 is at a low level, the contents of the counter 25 are selected by the selector 66 and set in the down counter 26 as they are. |
