| 摘要 |
PURPOSE:To obtain a memory circuit having a high speed and a high degree of integration, by combining a directory memory which is capable of reading and writing in a cycle with two different addresses and a data memory which performs reading or writing in a cycle. CONSTITUTION:The read data information is fed via a switch circuit 4 back to a directory memory 1 which can read and write read/write addresses RA, WA, etc. of two sets of addresses in a cycle from data memories 3a and 3b which can read or write in a cycle. Thus the memory 1 discriminates the memories 3a and 3b storing the latest information. The states of addresses and write enable signals to be applied to the memories 3a and 3b are controlled via an address switch circuit 2 in response to the result of above-mentioned distrimination of the memory 1. Then reading and writing are simultaneously carried out by a set of data memories having a low speed and high degree of integration. It is possible to obtain substantially a memory circuit having a high speed and high degree of integration by combining the memory 1 and the memories 3a and 3b. |
