Memory system handling a plurality of bits as a unit to be processed

摘要

A memory system for simultaneously extracting a desired block of data in response to an address specifying only the center bit of the block. The input address is modified through an arithmetic circuit wherein the address representing the center bit is added to and subtracted from to produce a plurality of addresses which are used to address a plurality of separate memory blocks. The outputs from the memory blocks are passed through a selection alignment matrix circuit which selects from the outputs of the memory blocks only those bits in the desired block of data and aligns those bits in a predetermined array. Bits other than those in the desired block of data are discarded.