PYTHAGOREAS ADDER OR SOLID STATE RESOLVER

摘要

A system for providing the square root of the sum of the squares of two input signals which can also be used to extract the common carrier component of the sin and cos output windings of a synchro differential resolver. Each input signal is applied to a divider means and to a multiplier means. The output of the divider means constitutes the other input to the multiplier means, and the output of both multiplier means are fed to an adder. The output of the adder constitutes the other input to the divider means. In addition, the output of the adder constitutes the square root of the sum of the squares of the two input signals or the common carrier component of the sin and cos output windings of a synchro differential resolver - depending on the application.