| 摘要 |
PURPOSE:To simplify the circuit constitution by connecting newly a MOS transistor (TR) to an input portion of a delay circuit and arranging a capacitor to constitute an input circuit thereby eliminating the need for an inverter circuit being cascade connection of plural stages. CONSTITUTION:The input circuit consists of an EMOS TR, DMOS TRs 1, 10 and capacitors C3, C4. When an input signal VIN fall down from VDD to zero V, since the capacitors C4, C3 and the DMOS TR1 are connected to a connecting point 51, the potential of a connecting point 50 rises to a voltage VDD with a delay of a potential at the connecting point 51. Thus, the input signal VIN is fed to a post-stage inverter with an inverted output with a delay from the connecting point 50 and an output signal VOUT is generated as a delayed output. |
