| 摘要 |
PURPOSE:To enable to suppress the resistance value of electrodes and wirings to low value by forming the electrode and wirings of the first layer of the same material as a gate electrode and improving the integration. CONSTITUTION:Si ions are implanted by an ion implantation method on a GaAs semi-insulating substrate 21, and an n type active layer 22 is formed. An alloy layer made of TiWSi is formed, patterned by an ordinary photolithographlic technique, and a gate electrode 23 is formed. With the electrode 23 as a mask an ion implantation method is applied, Si ions are implanted in high dosage, annealed, and an n<+> type source region 24 and an n<+> type drain region 25 are formed. A plasma etching method is used from above with an etchant of CHF3. A metal film 27 of Ti/Pt/Au is formed by a vapor deposition method. For example, with a photoresist film as a mask a technique such as ion milling is applied to perform a patterning of a metal film 27. |
