发明名称 |
A PIPELINED ANALOG-TO-DIGITAL CONVERSION SYSTEM |
摘要 |
A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register. |
申请公布号 |
DE3066147(D1) |
申请公布日期 |
1984.02.23 |
申请号 |
DE19803066147 |
申请日期 |
1980.06.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MERRILL, RICHARD BILLINGS;TERMAN, LEWIS MADISON;YEE, YEN SUNG |
分类号 |
H03M1/44;H03M1/00;H03M1/42;(IPC1-7):H03K13/08 |
主分类号 |
H03M1/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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