发明名称 SWITCHING METHOD OF PHASE-LOCKED LOOP CIRCUIT
摘要 PURPOSE:To ensure an assured phase locking action, by selecting a unit PLL circuit suited to an input data signal by means of plural unit circuits of different systems. CONSTITUTION:Both an A unit PLL circuit 11 and a B unit PLL circuit 12 perform pull-in actions in response to the input data signals to transmit synchronizing signals to a selector 13. A floppy disk 15a contains a normal revolution detecting hole. A light emitting element 15b is lit up, and the light quantity is detected by a photodetector 15c for each revolution of the disk. Then a detecting pulse signal is transmitted to a counter 14 via an amplifier 15d. The counter 14 transmits a counting signal to the selector 13 every times when it counts prescribed values 1-n. The selector 13 switches and selects the input signals given from the circuit 11 or circuit 12 and transmits a synchronizing signal as a reproduced clock signal. In such a way, it is possible to obtain a means to try repetitively the pull-in actions by means of plural unit PLL circuits. Thus, the mutual compensation of merits and demerits of various systems is ensured to obtain a reproduced clock signal.
申请公布号 JPS5933610(A) 申请公布日期 1984.02.23
申请号 JP19820142878 申请日期 1982.08.18
申请人 FUJITSU KK 发明人 OKADA TOSHIO;KARINO TOSHIO
分类号 G11B20/14;G11B20/10 主分类号 G11B20/14
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