| 摘要 |
<p>A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that each time a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charge procuring means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.</p> |
