True single error correction and multiple error detection system.

摘要

A system for true single error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. A first logic (40, 50) employs all syndrome bits in parallel inputs to determine the presence of a single bit failure for subsequent correction, and a second logic (70, 80, 90) receives all syndrome bits for detecting the presence of a multiple bit error in the data bits in the absence of a single bit failure.