Intersystem translation logic system

摘要

A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.