| 摘要 |
PURPOSE:To decrease the number of input/output pins, by forming an error correcting circuit system and a check bit generating circuit system on the same board. CONSTITUTION:A data control part 2 supplies the read data read out of a memory module through the 3rd data line 27 to perform an error correction, then delivers the read data to the 1st data line 25. At the same time, the part 2 adds an error correcting check bit to the data supplied to the line 25 via a bus receiver 5 and delivers the data to the 2nd data line 26. The line 26 is connected to the 1st and 2nd memory modules 3-1 and 3-2 via a buffer 6. The module addresses 24-1 and 24-2 and memory module control signals 23-1 and 23-2 are applied to the modules 3-1 and 3-2, respectively from a memory control part 1. |
