| 摘要 |
PURPOSE:To decrease the delay in generation and stopping of a modulation signal, by inputting an output of an oscillating circuit to a frequency dividing circuit, and inputting a control signal controlling the oscillation and stop of the modulation wave signal to a clear terminal of the frequency division circuit. CONSTITUTION:An output of the oscillating circuit 4 is inputted to the frequency division circuit 5, and a control signal is inputted to the clear terminal of the circuit 5. The frequency of the circuit 4 is denoted 484.5kHz and oscillated normally, the frequency division ratio of the circuit 5 is assumed as 1/ 16 and operated with the control signal (a), then the output frequency is divided in frequency and the desired 30kHz frequency is obtained. The circuit 5 operated with the signal (a) divides in frequency the oscillation output (b) and an output (c) is obtained. The delay (t) in the leading of oscillation is due to the delay in the clock inputted to the circuit 5 and within one wave of the oscillation output frequencies of the circuit 4. Since the normal oscillation frequency is a high frequency, the malfunction due to noise in the desired frequency does not take place. |
