| 摘要 |
PURPOSE:To ensure a high-speed DFT (discrete Fourier conversion) and to reduce the scale of an address control circuit, by using a periodical circulating address, and eliminating the division which is executed at the address control circuit. CONSTITUTION:A control circuit CONT performs the resetting, an increment of a counter and a register REG2 by the outputs of two binary counters C1 and C2 which store a degree (k) and an integer (n). The output of an adder ADD is fetched into a register REG2 and turned into the next address after an AND secured to a circulating cycle (register REG1). A binary data in which lower- order I-1 bits showing a circulating cycle N/2 (=2I<-1>) are all set at 1, and >=I bits are all set at 0 at the REG1 for setting circulating cycle. Then >=I bits of an adder output are all set at 0 by an AND circuit. Therefore, the addresses can be consecutively generated for a DFT which circulates in an N/2 cycle. |
