SYSTEM FOR SUPERPOSITION OF THE SUCCESSIVE STAGES OF THE TRANSFER OF DATA AMONG SEVERAL DATA PROCESSING UNITS

摘要

A control logic circuit (C) is provided in each unit such as processors and memories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQiL) of the unit itself and at the other input receives external calls (RQk) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.