发明名称 POLYPHASE CLOCK GENERATING SYSTEM OF INFORMATION PROCESSING DEVICE
摘要 <p>PURPOSE:To prevent a titled system from being affected by variations of power supply voltage and temperature, by basing on oscillation frequency of a stable fundamental frequency oscillator, and generating a phase difference. CONSTITUTION:An output oscillated by a fundamental frequency oscillator 7 to which frequency to be oscillated is indicated from an oscillation frequency commanding circuit 6 is shaped to a square wave by an FF8 and is inputted to a register 11. A phase difference determining oscillator 10 to which oscillation frequency integer times that of the fundamental frequency oscillator 7 is indicated by the oscillation frequency commanding circuit 6 is reset by an output of a differentiating circuit 9, is oscillated in synchronization with the fundamental frequency oscillator 7, and triggers the latch of registers 11, 12, 13 and 14. Accordingly, the registers 11, 12, 13 and 14 send out successively a square wave inputted from the FF8 at a delay time determined by the oscillation frequency of the phase difference determining oscillator 10, to terminals (a)-(d), and these waves are utilized as many clocks.</p>
申请公布号 JPS5930124(A) 申请公布日期 1984.02.17
申请号 JP19820140314 申请日期 1982.08.12
申请人 FUJITSU KK 发明人 IWATO MASATAKE
分类号 H03K3/64;G06F1/04;G06F1/06 主分类号 H03K3/64
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