发明名称 DIAGNOSTIC SYSTEM FOR FAULT OF LOGIC CIRCUIT
摘要 PURPOSE:To shorten the time required for diagnosing a fault by selecting a test input in which the part of a detected fault is the largest, with regard to each fault, and generating a fault diagnosing test input, by a means for adding a test input for a discrimination, if there is a group of faults, which cannot be discriminated by these test inputs. CONSTITUTION:A logic circuit has four pieces of input signal lines as signal lines, and 2<4>=16 kinds of inputs are generated by a logic circuit input value generating device 31. Subsequently, a fault table for showing a fault which can be inspected with respect to each of this input is obtained by a fault generating device 32. Next, from this fault table, a fault diagnosing test input is obtained by a fault diagnosing test input generating device 33. This fault diagnosing test input is sent to a tester 34, and the tester 34 applies actually this input to the logic circuit to be inspected 35. As a result, an obtained output signal value is sent from the tester 34 to a fault diagnostic device 36. In the device 36, an actual output signal value is collated with an expected value, and based on the degree of coincidence, the fault which does not occur at all is eliminated from the fault table against the fault diagnosing test input, and the fault is diagnosed.
申请公布号 JPS62159063(A) 申请公布日期 1987.07.15
申请号 JP19860000547 申请日期 1986.01.08
申请人 HITACHI LTD 发明人 OZAWA KUNIAKI;AKASHI KICHIZO
分类号 G01R31/317;G01R31/28;G01R31/319;G06F11/22 主分类号 G01R31/317
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