发明名称 TWO-DIMENSIONAL ADDRESS COUNTER CIRCUIT
摘要 PURPOSE:To count two-dimensional address easily in a high speed with a hardware circuit, by counting addresses by an adder and a latch. CONSTITUTION:A column index (n) of 2<n> from a column index converter 4 is converted to a bit pattern and is applied to a latch circuit 9 through the first adder 6, and the output of the circuit 9 is added to the adder 6 successively. A carry generator 8 is operated in accordance with a maximum value of addition outputs between the column index (n) and a line index (l) from the second adder 5, and the adder 6 is disconnected from the circuit 9, and the address in each column is counted. By this constitution, two-dimensional addresses are counted easily and quickly with hardware.
申请公布号 JPS5930286(A) 申请公布日期 1984.02.17
申请号 JP19820140871 申请日期 1982.08.11
申请人 MITSUBISHI DENKI KK 发明人 HARUOKA MASASHI
分类号 G06F12/06;G06F12/02;G11C8/00;(IPC1-7):11C8/00 主分类号 G06F12/06
代理机构 代理人
主权项
地址