发明名称 OPERATION PROCESSING SYSTEM
摘要 PURPOSE:To shorten the number of steps, and also to omit recorrect-processing, by providing a circuit for detecting which is necessary, substantial addition or substantial subtraction. CONSTITUTION:An augent or a minuend X is set to an X-register 1 through a line 101, and an added or a subtrahend Y is set to a Y-register 2 through a line 102, so that a code comes to the right end, respectively. Also, a line 100 is set to ''0'' and ''1'' at the time of addition and subtraction, respectively. Decimal addition and subtraction execute a classification of an operation to be executed to a code of a result and an absolute value, namely, bracketing of X+Y, X-Y or -X+Y, by the first step, and its operation is executed and a code is generated by the second step.
申请公布号 JPS5930143(A) 申请公布日期 1984.02.17
申请号 JP19820138535 申请日期 1982.08.11
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAOKA AKIRA;NAKAMURA KOUJI;HASHIMOTO MASAHIRO;WADA KENICHI
分类号 G06F7/494;G06F7/50;G06F7/508 主分类号 G06F7/494
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