发明名称 METHOD FOR TESTING SEQUENTIAL CIRCUIT
摘要 PURPOSE:To make it possible to detect the trouble of a logical element on a path, by employing a signal transmission path from the input of a sequential circuit to output thereof as a test unit. CONSTITUTION:In order to activate a path shown by a broken line, ''0'' is inputted to input terminals Ci0 and A1 and clock to a clock input terminal CLK while ''0'' to a reset input terminal RESET except on the initialization of a circuit. In the next step, a state transition diagram showing all combinations capable of being taken by the signal of a node representing the path and transition of the state inside the circuit on the path is fabricated. Q0-Q3 show four kinds of internal states capable of being taken by outputs F0 and F1. A0 is the input terminal of the path and S0, CO0 and S1 show nodes on the way of the path while an arrow shows the transition of the internal state. The signal pattern of time series inputted to the input terminal A0 may be constituted so as to perform all state transitions. By observing the signals of time series appearing in output terminals F0 and F1, all troubles of the logical element on the path can be detected.
申请公布号 JPS5930074(A) 申请公布日期 1984.02.17
申请号 JP19820140530 申请日期 1982.08.13
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 HAMAGUCHI SHIGETAKE
分类号 G01R31/28;G01R31/317;G06F11/22;G06F17/50 主分类号 G01R31/28
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