发明名称 JOSEPHSON LOGICAL NOT CIRCUIT
摘要 PURPOSE:To constitute a Josephson logical NOT circuit, especially an NOT latch circuit with a timing input, by using a current injection type as a basic switching gate. CONSTITUTION:Four Josephson junction elements (J1-J4) are used to form a closed loop 2. The closed loop 2 is provided with a pair of opposing circuit current terminals Pg-Pe, the closed loop 2 is divided into a left branch 2L and a right branch 2R by taking these two points as a boundary and two elements each are given in each branch. Further, the 1st and the 2nd control input terminals Pc1, Pc2 are provided among series elements J1-J4 in the branches 2R and 2L. The one circuit current terminal Pg is led to an input terminal G of a power supply current ig and the other circuit current terminal Pe is led to a common circuit line E in the closed loop constitution, respectively, and the 1st control input terminal Pc1 is led as a set input and signal input terminal S and the 2nd control input terminal Pc2 is led out as a timing input terminal T.
申请公布号 JPS5930329(A) 申请公布日期 1984.02.17
申请号 JP19820141213 申请日期 1982.08.14
申请人 KOGYO GIJUTSUIN (JAPAN) 发明人 NAKAGAWA HIROSHI;TAKADA SUSUMU
分类号 H03K19/195 主分类号 H03K19/195
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