| 摘要 |
<p>A virtual memory addresing system utilizing a paging substitution scheme, includes a processor (40) which provides a virtual address on a memory bus (44) together with a first control signal (PVT) which causes an address translator (42) to commence address translation. The virtual address is also provided to a memory interface unit (48) which causes the lower order address bits to be provided to the memory unit (50) whereby the memory addressing operation can commence. Upon completion of address translation, a second control signal (MAE) causes the translated real address to be latched into the memory interface unit (48) whereby the addressing operation of the memory unit (50) can be completed. The invention enables high speed virtual memory addressing to be achieved. </p> |
