发明名称 Electronic adder/subtractor in BCD 8421 code with decimal display
摘要 This parallel adder/subtractor has only one dual tetrad adder/subtractor per decade. This simplification is achieved by the fact that in each decade, a storage flip flop (6) is arranged which, when H potential is present at the output (y) is activated on the right when the line (c) has H potential for a short time. The output of this storage flip flop thus continuously has a H potential as a result of which the number 6 (LHHL) is also added in the second half of this selection according to Figure 8 if this adder/subtracter is set to addition and adding takes place and the output (y) had H potential in the relevant decade. During subtraction, this parallel adder/subtracter according to Figure 8 is also switched through as a result of which the number 6 (LHHL) is also subsequently subtracted in the decades which had H potential at their output (y). <IMAGE>
申请公布号 DE3222211(A1) 申请公布日期 1984.02.16
申请号 DE19823222211 申请日期 1982.06.12
申请人 MERKLE, PAUL, 7032 SINDELFINGEN, DE 发明人 MERKLE, PAUL, 7032 SINDELFINGEN, DE
分类号 G06F7/494;G06F7/50;(IPC1-7):G06F7/42 主分类号 G06F7/494
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