| 摘要 |
PURPOSE:To decrease the load of a processor, by providing a counter counting the change in a line signal in a subscriber circuit and counting the change in the signal with the hardware. CONSTITUTION:A line signal LS is inputted to an FF6 and the output of the FF6 is inputted to an FF7. Logical gates 11, 12 detect that the values of the FFs 6, 7 are the same and an FF8 is operative accordingly. For example, suppose that the period of a clock signal CK is 2ms, when the signal LS within 2ms is changed, the content of the FFs 6, 7 is not the same and no signal is outputted from the gates 11, 12. Thus, even if a short pulse due to the chattering enters the signal LS, it is eliminated. Then, the number of dial pulses is counted by inputting an output of the FF8 to a counter 9. On the other hand, a processor 1 fetches the content of the FF8 and counters 9-1-9-4 by transmitting a specific address to an address bus 2. |
