| 摘要 |
PURPOSE:To monitor a signal which is outputted from a PLL circuit without influencing a control system by comparing the counted value of a counter which inputs a signal to be applied to the PLL circuit with the preset upper and lower limit values, thereby stopping a control signal. CONSTITUTION:A frequency signal outputted from a frequency divider 7 is counted by a counter 14, inputted through a bus 13 to a muCPU2 at every prescribed period so as to discriminate whether it exceeds the preset upper or lower limit value or not. If it exceeds the limit value as a result of the discrimination, the muCPU2 outputs a gate lock signal to a gate circuit 12 when the excess occurs n times, thereby stopping a signal for controlling the gate of the inverter from the gate circuit 12. The frequency dividing set value and the upper or lower limit value of the counted value are set by using an operation panel 16. In this manner, the signal which is outputted from the PLL circuit can be monitored without influencing a control system. |
