发明名称 Programmable mode select by reset
摘要 A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.
申请公布号 US4432049(A) 申请公布日期 1984.02.14
申请号 US19800192157 申请日期 1980.09.29
申请人 SHAW, PERN;TIETJEN, DONALD L.;WILES, MICHAEL F. 发明人 SHAW, PERN;TIETJEN, DONALD L.;WILES, MICHAEL F.
分类号 G06F1/00;(IPC1-7):G06F3/00;H03K17/00 主分类号 G06F1/00
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