发明名称 MEMORY SLIP FREQUENCY DETECTING CIRCUIT
摘要 PURPOSE:To detect how many times memory slips occur within a prescribed time, by applying the 1st clock made of frequency-dividing a clock written in a memory of a staff synchronizing circuit with an FF to the 1st and the 2nd D type FFs. CONSTITUTION:A write clock (a) is applied to an FF1 to generate a frequency- divided clock, which is applied to the DFFs 3, 4. Further, a readout clock (b) is applied to an FF2 to generate a frequency-divided clock, which is applied to the DFF4 via an NOT circuit 11. When no memory slip exists, the DFF3 goes to 1 level and the DFF4 goes to 0 level, and when the slip occurs, the levels are inverted respectively. These outputs are delayed at delay circuits 5, 6, appied to EX-ORs 7, 8, and in applying the outputs to an OR circuit 9, a double pulse detecting the memory slip is outputted. The number of pulses is counted at a counter 10 ad divided by 2.
申请公布号 JPS5927651(A) 申请公布日期 1984.02.14
申请号 JP19820137564 申请日期 1982.08.07
申请人 FUJITSU KK 发明人 ITOU HIROKAZU;SUMIYA HIROYASU
分类号 H04J3/07;H04L25/05 主分类号 H04J3/07
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