发明名称 BUFFER MEMORY CONTROL CIRCUIT
摘要 PURPOSE:To exclude the undesired data and to deliver only desired data, by adding a control circuit in addition to a first-in/first-out (FIFO) memory and to discriminating the undesired data that is requested for pre-reading in the past to a main storage from the data desired at the present time point. CONSTITUTION:When a comparator 12 obtains the coincidence of comparison, a register 11 is set through a signal line 106 to fetch the data from an FIFO 10. The data fetched into the register 11 is sent to a device having a memory reading request through a route 107. Both data of the FIFO 10 and an additional information are not desired after the data is set to the register 11 and therefore taken away by an indication given from a signal of a signal line 108. When no coincidence is obtained at the comparator 12, the data is not set to the register 11. Therefore the data is invalidated and eliminated together with the additional information with an indication given from the signal of the line 108. As a result, no invalid data is sent to a device having a memory reading request.
申请公布号 JPS5928288(A) 申请公布日期 1984.02.14
申请号 JP19820136392 申请日期 1982.08.06
申请人 NIPPON DENKI KK 发明人 ISHII SATOSHI
分类号 G11C7/00;G06F12/08 主分类号 G11C7/00
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