| 摘要 |
PURPOSE:To shorten an instruction executing time, by using selectively either an instruction of a micro instruction generating circuit of a high speed by combination of a logical gate, or a micro instruction in a control storage, when executing a micro instruction. CONSTITUTION:A machine instruction stored in a main storage 1 is read out by an instruction register OPR2, is decoded by an instruction decoding circuit 3, and its output is inputted to a micro (mu) instruction ordering circuit 9. In the first cycle which follows decoding of a machine instruction of an executing cycle, the circuit 9 gives an instruction to a selector 8, selects a mu instruction generated at a high speed by a mu instruction generating circuit 5 consisting of a combined circuit of a logical gate, sends it to a mu instruction execution controlling circuit 10, and executes a mu instruction. At the same time, the circuit 9 sets an address of a control storage 4 to a control storage address register 6, and reads out a data of its address to a control storage data register 7 from the storage 4. After the second cycle, the circuit 9 gives an indication to the selector 8, selects an instruction of the register 7, sends it to the circuit 10, and executes a mu instruction of the control storage. |
