| 摘要 |
A phase lock loop employs a frequency discriminator having a relatively slow response to pull a voltage controlled oscillator into frequency lock with an input signal. After frequency lock the output of the frequency discriminator is nulled and a phase detector becomes effective to maintain phase lock. The frequency discriminator utilizes an operational amplifier to which both the input and oscillator signals are capacitively coupled through respective oppositely poled diode gates. A feedback capacitor, which is much larger than the input coupling capacitors, has charge transferred thereto fro m each coupling capacitors during alternate half cycles of the input and oscillator signals. The net charge across the feedback capacitor is a measure of the frequency difference between the input and oscillator signals, and is zero at frequency lock.
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