发明名称 CMOS FET INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To protect circuit elements by a method wherein a MOSFET in which a fixed voltage acting at a saturated region is impressed on the gate in the latch up state of an internal electronic circuit thereof is provided between a power source voltage supply terminal and the internal electronic circuit. CONSTITUTION:The MOSFET Q1 is provided between the external power source voltage supply terminal VDD and the internal power source voltage line of the CMOS circuit. The fixed voltage acting at the saturated region is impressed on the gate of the MOSFET Q1 in the latch up state of the CMOS circuit. Therefore, the MOSFET Q1 has latch up generated in the CMOS circuit, and when the power source voltage thereof decreases, it acts at the saturated region and then performs current clamp actions by the saturated current thereof.
申请公布号 JPS5925261(A) 申请公布日期 1984.02.09
申请号 JP19820133718 申请日期 1982.08.02
申请人 HITACHI SEISAKUSHO KK 发明人 MIYAMOTO NOBORU
分类号 H01L27/08;H01L27/02 主分类号 H01L27/08
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