| 摘要 |
PURPOSE:To increase the processing speed for converting instruction, by latching an integer type data directly to a register for mantissa part within an arithmetic unit for floating decimal point, and executing all processes within said arithmetic unit. CONSTITUTION:The integer type data read out of a main storage 10 is shifted up to the 2nd byte from the left within an aligner 20 and therefore latched to be closed to the left side of a register 40 for mantissa part. A complement controller 49 makes the latched data through a complement device 41 when the data is positive or 0 and then expresses the data in a positive number after a complement conversion when the data is negative. A constant generator 50 generates the code 0 with an integer or 0, then the code 1 or a constant of the exponent part when the data is negative respectively. Then, the data is erased after shifted 43 to the left by an amount equivalent to the number of 0 which are continuous at the upper place of the mantissa part latched to a register 42. At the same time, the exponent part latched to a register 46 undergoes a subtraction 47 by a shifted amount. Thus the obtained final result is written to a floating decimal point register 51 via a register 44. This can increase the processing speed for a converting instruction. |
