发明名称 REDUNDANCY CIRCUIT IN SEMICONDUCTOR MEMORY
摘要 PURPOSE:To realize a redundancy circuit which is very simple in circuit configuration and small in occupying area, by automatically forming a signal which designates a preliminary memory group from a signal change-over circuit, and outputting the signal to a preliminary decoder. CONSTITUTION:An address signal, by which a preliminary memory column 3s is selected against a preliminary Y-decoder 6 when a prescribed address signal is inputted. The preliminary Y-decoder 6, for example, is set to a condition where its output attains a high level (selecting level) when the signal supplied from the signal change-over circuit 5 attains low level. By the output of the selecting level of the preliminary decoder 6, all the outputs of a normal Y-decoder 2 are inhibited and a column switch which selects a preliminary column 3s is turned on. That is to say, when the output of the preliminary Y-decoder attains a high level, any memory columns containing defective bits in a normal memory array 3 are not selected and the preliminary column 3s is selected instead of the former.
申请公布号 JPS5924500(A) 申请公布日期 1984.02.08
申请号 JP19820131956 申请日期 1982.07.30
申请人 HITACHI SEISAKUSHO KK 发明人 SASAKI KATSUROU
分类号 G11C29/00;G11C29/04 主分类号 G11C29/00
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