Tristate transistor logic circuit with reduced power dissipation

摘要

A power-down network is included in a tristate TTL circuit to reduce power dissipation in the high impedance third state while permitting high switching speeds during bistate operation of the circuit. The power-down circuit includes a power-down transistor connected in series between the collector resistor and collector of the phase splitter transistor. The base of the phase splitter transistor is connected through a diode to the disabling gate. A first resistor having a significantly higher value than the collector resistor is connected between the base of the power-down transistor and the VCC terminal. When the circuit is in the high impedance state, the power-down transistor is turned off to interrupt current flow through the collector resistor, and a relatively high impedance current path through the first resistor to the disabling gate is substitute for an otherwise relatively low impedance current path through the collector resistor.