发明名称 |
Input buffer circuit |
摘要 |
In an input buffer circuit arrangement, a comparator compares a filtered input signal applied to one input with each of a first and a second reference value preset at the other input by a first setting circuit to produce a comparison output signal. According to the comparison output signal, a second setting circuit provides a third and a fourth reference value to one input of the comparator to obtain a noise-resistive characteristic.
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申请公布号 |
US4430618(A) |
申请公布日期 |
1984.02.07 |
申请号 |
US19810288373 |
申请日期 |
1981.07.30 |
申请人 |
NIPPONDENSO CO., LTD. |
发明人 |
MITSUEDA, HISAMI;TAMAKI, KAZUYOSHI;ARIYOSHI, HIROMI |
分类号 |
G01R23/06;H03K3/013;H03K3/0233;H03K5/08;H03K5/1252;(IPC1-7):H03K5/24;H03K17/16 |
主分类号 |
G01R23/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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