| 摘要 |
PURPOSE:To prevent a decrease in the output efficiency of a multi-processor system by dividing the address area of a common memory into plural areas by providing limited lock display signal lines for transmitting signals which indicate lock states of the respective address areas. CONSTITUTION:Plural processors Pi (i=1-n) is accessible to the common memory 3 through a common bus 2 under the control of a deciding circuit for the right of the use of the common bus. The address area in the memory 3 is divided into (m) areas, and signal lines 19-j (j=1-m) for transmitting limited lock display signals BLKj corresponding to the respective address areas and a limited lock generating circuit 18 which transmits and receives the signals BLKj to and from the Pi are provided. The circuit 18 decides on an address area wherein a lock signal 15 and an address signal from the Pi are limited and locked, and sends a request signal 20 for the use of the common bus to the circuit 4 when the bus request signal 9 is received from the Pi and the signal line 19-j corresponding to the determined address area is at a level L. Then when a permit signal 10 for the use of the bus is supplied from the circuit 4, the circuit 18 sets the signal BLKj to a level H to place the signal line 19-j in a locked state. |
