| 摘要 |
<p>A voltage detecting circuit (10) has a P-type FET (12) coupled in series with an N-type FET (14) between a first supply voltage node (16) and an input node (22), with the gates thereof coupled to a second supply voltage node (20). If the on-resistance of FET (14) is significantly greater than that of FET (12), the output node (18) will be substantially the first supply voltage when the input signal is absent, and the voltage of the input signal otherwise. A voltage translating circuit (40) has a P-type FET (42) coupled in series with an N-type FET (44) between a first supply voltage node (50) and an input node (56), with the gates thereof coupled to another input node (54). An N-type FET (46) is interposed between FET"s (42, 44) with the gate thereof coupled to yet another input node (58). Another N-type FET (48) is connected in parallel with FET"s (44, 46) between the output node (52) and input node (56), with the gate thereof coupled to a second supply voltage node (60). </p> |
