发明名称 MEMORY SYSTEM
摘要 PURPOSE:To attain easily the execution at rising, by providing a memory bus RAM/ROM switching control line and executing a prescribed specific program with an ROM and a usual changing program with an RAM. CONSTITUTION:The RAM2 and the ROM3 are connected to a CPU1 via a memory bus 10. The bus 10 consists of a data line 11, a memory address line 12 and a control line 13. The line 13 includes an RAM/ROM switching control line 14 to give an RAM/ROM switching control signal to the RAM2 and the ROM3. Thus, the RAM2 and the ROM3 are used distinctively with the RAM/ROM switching control signal when the RAM2 and the ROM3 are set for memory addresse 0-4k addresses, in taking the memory capacity of the RAM2 and the ROM3 as 4k-word.
申请公布号 JPS5920067(A) 申请公布日期 1984.02.01
申请号 JP19820128454 申请日期 1982.07.23
申请人 NIPPON DENKI KK 发明人 TAKITA HIROTATSU
分类号 G06F9/06;G06F1/00;G06F9/445;G06F12/06;G06F13/00 主分类号 G06F9/06
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