发明名称 FORMATION OF MULTILAYER WIRING
摘要 PURPOSE:To obtain a fine multilayer wiring without disconnections by a method wherein the upper layer metallic wiring is provided by depositing a metal having selectivity only on the exposed part of the lower layer metallic wiring by a CVD method arbitrarily. CONSTITUTION:A window is opened through a SiO2 film 2 on a Si substrate 1 whereon an element is formed, and then the lower layer wiring of a Al-1.5% Si alloy film 3 is provided. A PSG film 4 is superposed by a CVD method, a micro hole is opened, and then a W film 5 is formed on the Al-Si alloy 3 by a pressure reduction CVD method under the condition of H2 15l/min, WF6 30cc/ min, substrate temperature 400 deg.C, deposition pressure 40Pa, and deposition speed 15nm. This condition causes deposition only on the Al-Si alloy 3, not on the PSG film 4. Next, the upper layer wiring is formed by sputtering an Al film 6. This constitution enables perfect connection even when the diameter of the through hole is as fine as 2mum or less, and accordingly easily obtain the multilayer wiring of a fine structure without disconnections.
申请公布号 JPS5918659(A) 申请公布日期 1984.01.31
申请号 JP19820127510 申请日期 1982.07.23
申请人 HITACHI SEISAKUSHO KK 发明人 SAIDA HIROJI;KIKUCHI AKIRA;SATOU AKIRA;KOGIRIMA MASAHIKO
分类号 H01L23/522;H01L21/28;H01L21/285;H01L21/768 主分类号 H01L23/522
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