METHOD AND CIRCUIT ARRANGEMENT FOR THE MACHINE EXECUTION OF THE COMMANDS OF DATA PROCESSING COMPUTERS

摘要

In a computer which includes function units interconnected by a bus system there is a first type of instruction which selects one function unit and orders the performance of an internal function and a second type of instruction which selects two function units for the interchange of data through the bus system and orders the data receiving function unit to perform an internal function using the transferred data. The execution period of the second instruction type has a first part during which the first function unit is ordered to transmit data, a second part during which the data are transferred to the bus system and a third part during which the other function unit receives the transferred data. The design of the bus system makes possible the simultaneous performance of the second and third parts. The instructions are successively obtained by a fixed-cycle reading of an instruction memory and are transferred therefrom through the bus system to the function units. The execution period for an instruction of the first type and for the first part of an execution period part of the second type, respectively, are finished during the read phase of that instruction. The simultaneous performance of the second and third part of an execution period for an instruction of the second type are finished during the read phase of the following instruction.