| 摘要 |
PURPOSE:To shorten memory access time, by providing a buffer circuit which gives priority to writing and enqueues reading only when the writing and reading are produced at the same time and the same address. CONSTITUTION:The 1st RAM21 is a memory circuit having only even-numbered addresses and the 2nd RAM22 is a memory circuit having onlt odd-numbered addresses. Input data are written in the order of the RAMs 21, 22, 21- successively. The reading is carried out regardless of the writing, but only when the writing and reading coincide at an even-numbered or odd-numbered address, read pulses are enqueued temporarily to perform the writing preferentially. Consequently, the RAMs are reduced in capacity and the input data are written and read completely independently. |
