| 摘要 |
<p>PURPOSE:To prevent surely the malfunction due to a PNP-N circuit at a read time, by controlling the PNPN circuit by a gate circuit. CONSTITUTION:A gate circuit 8 is added to the normal PNPN circuit to control the intersection between the collector of a PNP transistor (TR) and the base of an NPN (TR) of the PNPN circuit, and the PNPN circuit can be always inactivated surely when a power source voltage VCC is turned on. That is, when the voltage VCC is turned on, a TR Qc is turned on to make the base of the NPN TR of the PNPN circuit low-level, and therefore, the NPN TR cannot be turned on, and the PNPN circuit is inactivated surely to prevent the malfunction. At a write time, the TR Qc is turned off because the voltage VCC is not supplied, and the PNPN circuit performs the same operation as the normal PNPN circuit. That is, the malfunction due to the PNPN circuit is eliminated at a read time, and the normal write is possible at a write time.</p> |
