发明名称 VOLTAGE LEVEL ADJUSTER
摘要 PURPOSE:To widen the operating range and to reduce the power consumption by providing a storage circuit comprising MOSFETs of complementary connection. CONSTITUTION:The storage circuit is constituted by connecting crossingly each gate and each drain of P channel FETs 18, 19 and N channel FETs 21, 22. P channel FETs 20, 22 are connected in parallel with the FETs 21, 22 and P channel FETs 16, 17 are connected in series with the FETs 18, 19. An input signal is applied to the gate of the FETs 16, 17 and to the gate of the FETs 20, 22 via capacitors 24, 25. Thus, a signal converting the VSS2 level of the input signal to the VSS1 level is obtained from an output terminal 30. Further, since the storage circuit is provided, the operating range is made broader from a low to a high speed.
申请公布号 JPS5916416(A) 申请公布日期 1984.01.27
申请号 JP19820126145 申请日期 1982.07.20
申请人 CITIZEN TOKEI KK 发明人 YAMAGUCHI SHIZUO;SEKIYA FUKUO
分类号 H03K19/0185;H03K3/356;H03K5/02;H03K19/018 主分类号 H03K19/0185
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