| 摘要 |
PURPOSE:To enable to compose a load of low power type by connecting in series a plurality of FETs which are comonly connected at gates between a power source and a drive transistor. CONSTITUTION:Load FETs 2 connects commonly at the gates are inserted in series between a power source 2 and a drive FET3, and a load FET is further associated in parallel. In this case, one type of two fundamenta load FETs are used to be equivalent to three types of FETs. Accordingly, one FET can be reduced from the fundamental cell of LSI of master-slice type, and can be advantageously integrated. When the two fundamental loads FETs of different characteristics are used four load FETs can be selected, and when three are used, seventeen load FETs can be selected. Further, when depletion type FETs connected commonly at the gates are connected in advance in series with each other, and altered at the connecting position to the power source, the capacity of the load FETs can be varied, thereby facilitating the acceleration of the speed and the conversion to low power. |
