| 摘要 |
PURPOSE:To prevent the dissidence between a cache memory and a main memory and to obtain easily a virtual storage device of desired connection, by providing an effective display part within a cash memory and controlling said display part with a main processor, an input/output device, etc. CONSTITUTION:An AND gate 24 is opened via a directory 18, a comparator 20, etc. and in response to the indications which are stored in an address register 13 and a function register 14 of a cache memory 15 from a main processor. Then gates 33 and 34 are opened with a cache signal given via the gate 24 if no cache bit exists, and an access is given to a main storage device to store the read-out data into a cache memory main body 19 as well as to display the validity at a display part 70 by means of an effective flag corresponding to the relevant address. This display is invalidated in the same way via the main processor of an I/O. Thus it is possible to obtain easily a virtual storage processor in which a main processor, a cache memory, an address converter and a main memory are connected successively without having no discordance between the cache memory and the main memory. |
