| 摘要 |
PURPOSE:To enable the simultaneous reading of contents of a pair of memories and to decrease the arithmetic processing time, by giving accesses to these memories storing the same data in the same address with exchange of addresses in case an error arises. CONSTITUTION:The address of an address register 5a or 5b is selected by address control circuits 2a and 2b which are controlled by a control circuit 6. Then a simultaneous access is given to memories 1a and 1b having the same information written to the same address. When an error is detected by error detecting circuits 4a and 4b for the read data given via data control circuits 3a and 3b, the circuits 2a and 2b are controlled via the circuit 6 to have an exchange of address which gives accesses to the memories 1a and 1b. As a result, it is always possible to read in parallel and simultaneously correct data out of a pair of memories. This can decrease the arithmetic processing time which is based on the read data. |
