| 摘要 |
PURPOSE:To converge a system including an automatic equalizer and a carrier detecting PLL rapidly and stably in an initial training sequence, by off-setting the phase error of the carrier in a base band. CONSTITUTION:When the absolute phase of a carrier is detected under the status that a switching circuit 50 is connected to the ''0'' side and then the switching circuit 50 is turned to the contact 1 side by a switching signal S from a sequence controlling circuit after completing alternation, the training of the equalizer or the like is started by the false random sequence of binary symbols and the phase of the carrier is controlled by a quantizer 12, a divider 14 and an imaginary part selecting part 18. In an output signal from a divider 102 or a substitutive multiplier, the value of the imaginary part (y) is outputted 52 as a phase difference DELTAtheta when the real part (x) is positive (or zero), and the value obtained by subtracting the value of the imaginary part (y) from pi is outputted as the DELTAtheta when the real part (x) is negative (or zero). |
