发明名称 Method of and system for evaluating bit errors in testing a signal path
摘要 In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.
申请公布号 US4428076(A) 申请公布日期 1984.01.24
申请号 US19810330719 申请日期 1981.12.14
申请人 WANDEL & GOLTERMANN GMBH & CO. 发明人 SCHUON, EBERHARD
分类号 H04L1/24;H04L25/04;(IPC1-7):H04B17/00;H04L1/00 主分类号 H04L1/24
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