发明名称 PROCESSING CIRCUIT OF INTERRUPTION SIGNAL
摘要 PURPOSE:To decrease the number of terminals, by having distinction between the normal interruption and the monitor interruption from the pulse width of the interruption input signal which is applied to an interruption input terminal. CONSTITUTION:When an interruption signal which is active (L level) during a period of a clock CK2 is applied to an interruption input terminal 21, an interruption flag register RG22 is set at a time point when the interruption signal has a fall. The output of a monitor interruption detecting circuit 23 is kept at L level. Therefore an interruption request flag 3 is set but a monitor interruption request flag 13 is not set. Then the process proceeds to a normal interruption processing sequence when an instruction under execution is over. At the same time, the RG22 is reset by a normal interruption reception signal 4. When the CK2 is impressed when the input signal of the terminal 21 is set inactive (H level) after a prescribed time elapses and the flag 3 is set, the circuit 23 is set at H level to set a monitor interruption request flag RG24 and then the flag 13. Thus the priority is given to the monitor interruption. Then the RG24 is reset when a monitor interruption accepting signal 14 is supplied.
申请公布号 JPS5911424(A) 申请公布日期 1984.01.21
申请号 JP19820121787 申请日期 1982.07.12
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MATSUZAKI TOSHIMICHI;SAKAO TAKASHI;UEDA KATSUHIKO;SUZUKI TOSHIAKI
分类号 G06F9/48;G06F13/24 主分类号 G06F9/48
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