| 摘要 |
<p>PURPOSE:To output a long period pulse without converting a storage part to large capacity, by masking a pulse outputted from a pulse generating circuit of a pre-stage, by a pulse outputted from its own pulse generating circuit. CONSTITUTION:A counter 101 outputs a count signal wherever a pulse 104 is inputted. This output designates successively an address in an ROM 102, and outputs each different data in accordance with an address. This output is stored in each separate register in a register 103, and is outputted whenever the pulse 104 is inputted to said register. A pulse generating circuit of the following stage also executes the same operation by a pulse 107. Accordingly, an AND gate 113 masks a pulse 106 when a pulse 111 is not inputted, therefore, a pulse shown by 115 is outputted. Also, an AND gate 114 masks the pulse 106 since a pulse 112 is not outputted, and does not output a pulse as shown by 116.</p> |
